1. Field of the Invention
The present invention relates, in general, to a reference voltage generating circuit formed on a semiconductor substrate, and, in particular, to a reference voltage generating circuit which is stabilized by temperature compensation. The present invention has a particular applicability to an internal voltage converting circuit in a semiconductor device.
2. Description of the Background Art
In the semiconductor devices, it has been desired to provide stabilized reference voltage generating circuits which are not affected by the change of the ambient temperature. However, the characteristics of the semiconductors are generally liable to be affected by the change of the ambient temperature. It is, therefore, difficult to stabilize output voltages supplied from the reference voltage generating circuits.
MOS transistors have been used in various semiconductor memory devices such as DRAMs (dynamic random access memories) because of their suitability to high integration and other reasons. Bipolar transistors have been widely used for forming the reference voltage generating circuits on the semiconductor substrates. In the manufacturing steps for manufacturing the semiconductor devices formed of MOS transistors, however, addition of steps for forming bipolar transistors unpreferably complicates the manufacturing steps. This means that it has been generally desired to form the stable reference voltage generating circuits formed of the MOS transistors on the semiconductor substrates.
The reference voltage generating circuits can be applied, for example, as internal voltage converters in the DRAMs. Since the DRAM is generally formed of a large number of CMOS transistors, the stable internal voltage converters formed of the CMOS transistors, i.e., stable reference voltage generating circuits have been desired. In general, it is noted that the invention is preferably applied to the semiconductor device requiring a reference voltage generating circuit formed of field effect transistors.
FIG. 14 is a schematic diagram showing an example of a reference voltage generating circuit in the prior art. Referring to FIG. 14, a reference voltage generating circuit 211 includes a constant current source 27 and a PMOS transistor 28 connected in series between a power supply potential Vcc and the ground. The constant current source 27 and transistor 28 have a common connection node No through which a reference voltage, i.e., output voltage Vo is supplied. The transistor 28 has its gate and drain connected together.
FIG. 16 is a characteristic diagram showing relationship between a voltage across the gate and source of the transistor 28 in FIG. 14 and a drain current thereof. Referring to FIG. 16, the abscissa indicates the voltage V.sub.GS (volt) across the gate and source, and the ordinate indicates the drain current (A/.mu.m) per channel width of 1 .mu.m. The characteristics of the transistor 28 shown in FIG. 14 are represented by characteristics A indicated by lines LA30 and LA100 in FIG. 16. The line LA30 indicates the characteristics at the ambient temperature of 30.degree. C., and the line LA100 indicates the characteristics at the ambient temperature of 100.degree. C.
Assuming that the constant current source 27 shown in FIG. 14 supplies the drain current of 10.sup.-7 (A/.mu.m), the gate-source voltage V.sub.GS of transistor 28 is Va (=-1.0) at the ambient temperature of 30.degree. C. and is Vb (=-0.94) at the ambient temperature of 100.degree. C. The reference voltage generating circuit 211 shown in FIG. 14 supplies the output voltage Vo of .vertline.Va.vertline.=1.0 V at the ambient temperature of 30.degree. C. and of .vertline.Vb.vertline.=0.94 V at the ambient temperature of 100.degree. C. Therefore, a voltage fluctuation ratio of the reference voltage generating circuit 211 is (1.0-0.94)/1.0.times.100=6%.
FIG. 15 is a schematic diagram showing another example of the reference voltage generating circuit in the prior art. A reference voltage generating circuit 212 shown in FIG. 15 is disclosed in a paper entitled "A TUNABLE CMOS-DRAM VOLTAGE LIMITER WITH STABILIZED FEEDBACK AMPLIFIER" (M. Horiguchi et al., 1990 Symposium on VLSI Circuits, pp 75-76; IEEE).
Referring to FIG. 15, the reference voltage generating circuit 212 includes two constant current sources 33 and 34, diode-connected PMOS transistors 30 and 31 and a differential amplifier 32. Transistor 30 has its gate and drain connected together. The constant current source 33 and the transistor 30 have a common connection node N2 which is connected to a noninverted node of the differential amplifier 32. The constant current source 34 and the transistor 31 have a common connection node N1 which is connected to an inverted node of the differential amplifier 32. An output node of the differential amplifier 32 is connected to the gate of transistor 31.
The transistor 31 has such gate-source voltage and drain current characteristics as represented by characteristics A in FIG. 16. Transistor 30 has such gate-source voltage and drain current characteristics as represented by characteristics B in FIG. 16. The characteristics B are represented by line LB30 indicative of the characteristics at the ambient temperature of 30.degree. C. and line LB100 indicative of the characteristics at the ambient temperature of 100.degree. C.
The reference voltage generating circuit 212 shown in FIG. 15 operates as follows. When the potential of node N1 is higher than that of node N2, the differential amplifier 32 supplies the lower output voltage. Therefore, the transistor 31 is turned on with a lower ON-resistance, and thus the potential of node N1 reduces. When the potential of node N2 is higher than that of node N1, the differential amplifier 32 supplies the higher output voltage. Therefore, the transistor 31 is turned on with a higher ON-resistance, and thus the potential of node N1 rises. As a result, potential at each of nodes N1 and N2 is always kept constant.
It is assumed that the transistors 30 and 31 receive a drain current of 10.sup.-7 (A/.mu.m) from the constant current sources 33 and 34, respectively. At the ambient temperature of 30.degree. C., the potential of node N1 has a value of Vo+.vertline.Va.vertline. in accordance with the characteristics in FIG. 16, and the potential of node N2 has a value of .vertline.Vc.vertline..
As described above, the potentials of nodes N1 and N2 are controlled to be equal to each other, so that relationship of .vertline.Vc.vertline.=Vo+.vertline.Va.vertline. reference voltage generating circuit 212 supplies the output voltage Vo of .vertline.Vc.vertline.-.vertline.Va.vertline. at the ambient temperature of 30.degree. C. Similarly, the output voltage Vo at the ambient temperature of 100.degree. C. is Vo=.vertline.Vd.vertline.-.vertline.Vb.vertline. in accordance with the characteristics in FIG. 16.
As can be seen from FIG. 16, the values of .vertline.Vc.vertline.-.vertline.Va.vertline. and .vertline.Vd.vertline.-.vertline.Vb.vertline. are nearly equal to each other. Therefore, the output voltage Vo is maintained substantially at a constant value regardless of the change of the ambient temperature.
The reference voltage generating circuit 212 shown in FIG. 15 requires the PMOS transistors 31 and 30 having the characteristics A and B shown in FIG. 16. In order to manufacture the PMOS transistors 30 and 31 having the different characteristics A and B, it is necessary to increase a quantity of n-type impurity doped in a channel region of the transistor 30 in the manufacturing steps of the semiconductor device. Therefore, as compared with a case that the circuit is formed of MOS transistors having common characteristics only, the number of steps for manufacturing the reference voltage generating circuit 212 increases, and thus the manufacturing cost of the semiconductor device increases.
FIG. 17 shows simplified manufacturing steps for MOS transistors having channel regions of different impurity concentrations. First, in a step shown in FIG. 17(a), a field oxide film 301 for separating elements is formed on a semiconductor substrate 300, and then n-type impurities at a low concentration are implanted thereinto. At a next step shown in FIG. 17(b), a resist 302 is formed on one of the implanted regions, and n-type impurities at a higher concentration are further implanted into the other implanted region. Thereby, the p-type impurity regions 303 and 304 having different impurity concentrations are formed.
In the step in FIG. 17(c), gates 305 and 306 for the MOS transistors are formed with polysilicon. In a step in FIG. 17(d), n-type impurities are implanted for forming sources and drains of MOS transistors. As a result, the transistor 31 having the characteristics A shown in FIG. 16 and the transistor 30 having the characteristics B are formed on the semiconductor substrate 300.
As can be seen from FIGS. 17(a)-(d), additional steps are required for forming MOS transistors 30 and 31 having the different characteristics A and B, respectively.
FIG. 18 is a circuit diagram showing still another example of a reference voltage generating circuit in the prior art. A reference voltage generating circuit shown in FIG. 18 is disclosed in a paper entitled "Temperature-Compensation Circuit Techniques for High-Density CMOS DRAMs" (D. S. Min et al., pp 125-126).
Referring to FIG. 18, a reference voltage generating circuit includes a current source 311, a diode-connected PMOS transistor 312, a differential amplifier 313, PMOS transistors 314 and 315, a resistor 316 formed of polysilicon and a driver 317 of a voltage follower type. The current source 311 and PMOS transistor 312 form a reference voltage generator.
The reference voltage generating circuit shown in FIG. 18 can be applied as an internal voltage converter (IVC) in the DRAM. The reference voltage generating circuit shown in FIG. 18 uses the resistor 316 formed of polysilicon for compensating the influence on the output voltage Vo by the change of the ambient temperature. It is noted that the polysilicon resistor 316 is useful for the temperature compensation, but it is difficult to form the polysilicon resistor having a stable resistance in the manufacturing steps of the semiconductor device. Specifically, the resistance of polysilicon resistor 316 often changes in accordance with the manufacturing conditions, and thus the output voltage Vo is liable to change.